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\newcommand{\outsr}{\ensuremath{\mathrm{OUT/\overline{SR}}}}
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\title{Testing the H1 CST Decoder Chip}
\author{\sc Benno List}
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\begin{document}
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\begin{center}
{\bf \boldmath \LARGE Testing the H1 CST Decoder Chip}\\
\vspace{0.5cm}
{\sc \Large Benno List}\\
\vspace{0.5cm}
{\Large ETH Z\"urich, IPP}\\
\vspace{0.5cm}
{\large 29.5.2000, 9.3.2001}\\
\end{center}
\vspace{0.5cm}
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\section*{Reset Test}
%         ==========

{\bfseries Program:} {\tt test1.src}

{\bfseries What is tested:} How much time is needed to fast clear the
  whole shift register.
  
{\bfseries Signals to look at:} OUT8 (last bit of the current supply
register)

{\bfseries What to do:} Run the program and vary the clock speed of the
pattern generator until OUT8 does not go to 0 any more.
The time of one external clock cycle is then the minimum time for a fast
reset.

{\bfseries How it works:} After an initial reset, the program goes into
a loop. In this loop, the shift register is first filled with ones
(only bits 1--4 are set to 0). After that, a fast reset is done.
If the fast reset signal is too short, the last bit of the shift
register will not go to 0 anymore.

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\section*{Output ModeTest}
%         ==========

{\bfseries Program:} {\tt test2.src}

{\bfseries What is tested:} Switching between sample and output mode
  
{\bfseries Signals to look at:} SPHI1, SPHI2, SBI, RPHI1, SPHI2, RBI,
compare to CLK1, CLK2, BIN

{\bfseries What to do:} 

\begin{itemize}
\item Check the relative timing between SPHI1/RPHI1
      and CLK1, SPHI2/SPHI2 and CLK2, SBI/RBI and BIN.
\item RBI should show a sequence $0-1-00-1-0-1-000$ every second time 
      when \outsr\ is 1.
\item SBI should show a sequence $0-1-0-11-0-111-0$ every second time 
      when \outsr\ is 1.
\item Check the function of the RBE signal.
\end{itemize}
 
\begin{figure}[h]
  \setlength{\unitlength}{1mm}
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%  \fbox{
  \begin{picture}(150,55)
    \put(0, 0){\epsfig{file=test2-r.eps,width=70mm}}
    \put(80, 0){\epsfig{file=test2-s.eps,width=70mm}}
  \end{picture}
%  }
  \end{center}
\caption[]{Scope view of the $R\Phi1$, $R\Phi2$, and $RBI$ signals
(left) and the  $S\Phi1$, $S\Phi2$, and $SBI$ signals (right) for
TEST2.
  }
\label{figure-test2}
\end{figure}  


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\section*{APC Signals Register TES}
%         ========================

{\bfseries Program:} {\tt test3.src}

{\bfseries What is tested:} The signals from the APC signals register.
  
{\bfseries Signals to look at:} SBI, RESET, IS, SR, R12, CS, SEB, LE,
SIGNAL12, SIGNAL13, SIGNAL14, SIGNAL15, SIGNAL16

{\bfseries What to do:} Look on SBI, two zeroes indicate the start of
the pattern. Look at the other signals in turn signals and identify
them by their bit patterns:

\begin{tabular}{l|l|l|l}
Pin & Bit & Name & Pattern \\
\hline
14 &  5 & Reset     & $111111-000$  \\
15 &  6 & IS        & $1111-0-1-000$ \\
16 &  7 & SR        & $111-0-11-000$ \\
18 &  8 & R12       & $111-00-1-000$ \\
19 &  9 & CS        & $11-0-111-000$ \\
29 &  10 & SEB      & $11-0-1-0-1-000$ \\
13 &  11 & LE       & $11-00-11-000$ \\
63 &  12 & SIGNAL12 & $11-000-1-000$ \\
57 &  13 & SIGNAL13 & $1-0-1111-000$ \\
58 &  14 & SIGNAL14 & $1-0-11-0-1-000$ \\
59 &  15 & SIGNAL15 & $1-0-1-0-11-000$ \\
62 &  16 & SIGNAL16 & $1-0-1-00-1-000$ \\
\end{tabular}
 
\begin{figure}[h]
  \setlength{\unitlength}{1mm}
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%  \fbox{
  \begin{picture}(150,110)
    \put(0, 55){\epsfig{file=test3-1.eps,width=70mm}}
    \put(80,55){\epsfig{file=test3-2.eps,width=70mm}}
    \put(0,  0){\epsfig{file=test3-3.eps,width=70mm}}
    \put(80, 0){\epsfig{file=test3-4.eps,width=70mm}}
  \end{picture}
%  }
  \end{center}
\caption[]{Scope view of the signals for TEST3:\\
upper left: Reset, IS, SR;
upper right: R12, CS, SEB \\
lower left: LE, Signal12, Signal13;
lower right: Signal15, Signal16

  }
\label{figure-test3}
\end{figure}  

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\section*{Calibrate Register Test}
%         ======================= 

{\bfseries Program:} {\tt test4.src}

{\bfseries What is tested:} The calibrate register

{\bfseries Signals to look at:} SBI, Calibrate

{\bfseries What to do:} Observe the Calibrate output.
It should show a pattern 0-1-00-1-000-1-0000-1-00000-1-000000-1-0000-1
  
\begin{figure}[h]
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    \put(0, 0){\epsfig{file=test4.eps,width=70mm}}
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  \end{center}
\caption[]{Scope view of the $S\Phi1$, $S\Phi2$, $SBI$, and $CAL$ signals for
TEST4.
  }
\label{figure-test4}
\end{figure}  
 
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\section*{Control Register Test}
%         =====================

{\bfseries Program:} {\tt test5a.src}

{\bfseries What is tested:} The control register

{\bfseries Signals to look at:} SBI, SW

{\bfseries What to do:} Connect a series of resistors to SW1 to SW8 such
that the voltage on SW1 is $V_{DD}/8$, on SW2 is $2 V_{DD}/8$, and so on
up to SW8 with $V_{DD}$.
Look at SW. It should show a staircase pattern.
   
\begin{figure}[h]
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    \put(0, 0){\epsfig{file=test5.eps,width=70mm}}
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  \end{center}
\caption[]{Scope view of the SW signal for
TEST5A.
  }
\label{figure-test5a}
\end{figure}  
 

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\section*{Current Supply Register Test}
%         ============================

{\bfseries Program:} {\tt test6.src}

{\bfseries What is tested:} the current supply register

{\bfseries Signals to look at:} The current source output and DAC8

{\bfseries What to do:} Connect a voltage to $V_{DAC}$.
Monitor the current source output. It should show a staircase pattern
with the following values:
0, 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 112, 120, 124, 126,
127, 0.
At the end of the staircase, OUT8 should show a ``1''.

  

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\section*{Latch Function Test}
%         ==========

{\bfseries Program:} {\tt test7.src}

{\bfseries What is tested:} The latch functionality of the APC signals
register.

{\bfseries Signals to look at:} Calibrate, SW, Current source, DAC8

{\bfseries What to do:} 
\begin{itemize}
\item Check the calibrate signal. It must stay at 0.
\item Connect a resistor chain to SW1\dots SW8. Check SW. It must not
      show any activity.
\item Connect a voltage to $V_{DAC}$. Observe the current source and
      DAC8. No changes must be visible.
\end{itemize}

{\bfseries How it works:} The program loop clears the shift register and
transfers its contents to the APC signals register, the calibrate
register, the control register, and the current supply register.
Then it sets the shift register to various bit patterns which should not
be transferred to the buffers. 
  


% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% \section*{}
% %         ==========
% 
% {\bfseries Program:} {\tt test.src}
% 
% {\bfseries What is tested:} 
% 
% {\bfseries Signals to look at:} 
% 
% {\bfseries What to do:} 
% 
% {\bfseries How it works:} 
%   
% \end{tabular} 


 
\begin{figure}[p]
  \setlength{\unitlength}{1mm}
  \begin{center}
  \begin{picture}(100,200)
    \put(0, 0){\epsfig{file=decoderdmill-final-color-labeled.ps,height=200mm,
    bbllx=102,bblly=13,bburx=484,bbury=813,clip=}}
  \end{picture}
  \end{center}
\caption[]{Layout of the DMILL decoder.
  }
\label{figure1}
\end{figure}  
 
\begin{figure}[htb]
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  \begin{picture}(150,80)
    \put(0, 0){\epsfig{file=decoderdmillfinal-overview.eps,width=150mm}}
  \end{picture}
  \end{center}
\caption[]{Overview over the decoder chip.

The abbrevations stand for:
{\bfseries Curr. S.}: current source,
{\bfseries CR}: control register,
{\bfseries CSR}: current supply register,
{\bfseries APC SR}: APC shift register,
{\bfseries Diff Inp.}: differential inputs,
{\bfseries Out Drv}: output drivers,
{\bfseries Input Protect.}: input protection.
 }
\label{figure2}
\end{figure}  
 
\begin{figure}[htb]
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    \put(0, 0){\epsfig{file=decoderschematic.eps,width=150mm,
    bbllx=60,bblly=412,bburx=513,bbury=735,clip=}}
  \end{picture}
  \end{center}
\caption[]{Schematic of decoder.
  }
\label{figure3}
\end{figure}  
 
\begin{figure}[p]
  \setlength{\unitlength}{1mm}
  \begin{center}
%  \fbox {
  \begin{picture}(150,170)
    \put(-10, 0){\epsfig{file=decoderfinal-bondplan-test.eps,width=170mm,
    bbllx=38,bblly=172,bburx=542,bbury=677,clip=}}
  \end{picture}
%  }
  \end{center}
\caption[]{Bonding scheme for the decoder on the test chip carrier.
  }
\label{figure4}
\end{figure}  

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\end{document}

